Symposium A3. Advanced Interconnect and Dielectric Materials Innovative Packaging Methodology for Post CMOS Era

Jenn-Ming SongNational Chung Hsing University
Chih Chen National Yang Ming Chiao Tung University
Chih-Ming ChenNational Chung Hsing University
Albert T. WuNational Central University
Cheng-En HoYuan Ze University
Shih-kang LinNational Cheng Kung University
Scope & Topics

The electronics industry is nearing the limits of traditional CMOS scaling. The request in capability and functionality of the devices is drastically increasing. Regarding emerging applications of electronic devices, such as healthcare, Industry 4.0, automotive, and so on, revolutionary changes to interconnect and packaging technologies for smarter usage are progressing. The scope of area A3 covers leading edge developments and technical innovations across interconnects and packaging spectrum. Topics ranging from materials and processing, assembly and manufacturing, characterization and applied reliability are included. The technical sessions under area A3 will provide a perfect opportunity to communicate, interact, and exchange technical ideas for anybody in the field of interconnect and packaging technologies. Papers related to interconnect materials, processes and devices are solicited including (1) Interconnects & Dielectrics, Cu/low-k and those applied in TSV, microbumps, wafer level packaging and system-in-package; (2) Sensor/MEMS/optical integrations; (3) Power/Thermoelectronics packaging; (4) Substrates for different level packages, and interfaces including interactions and intermetallics; (5) Emerging Technologies and Materials; (6) Phase stability and reliability phenomena, e.g. electromigration, thermomigration, and their physics. Symposium topics will include (but not limited to):

  1. Interconnects & dielectrics
  2. Heterogeneous & photonic integration
  3. Power and thermoelectronic packaging
  4. Substrates and interfaces
  5. Emerging technologies and materials
  6. Phase stability and reliability